MN-Core Architecture
MN-Core 2 hardware architecture and how it differs from GPUs.
VLIW / SIMD Architecture
MN-Core adopts a VLIW (Very Long Instruction Word) instruction format with massive SIMD Processing Elements (PEs). Because operations are explicitly scheduled in each instruction word, programmers and compilers have fine-grained control over hardware resources.
No Cache, Explicit Data Movement
MN-Core has no hardware cache. Without cache interference or speculative behavior, execution is fully deterministic — the performance you measure in simulation is the performance you get on hardware.
Hierarchical Memory (L2BM / L1BM / MAB / GRF)
A multi-tier on-chip memory hierarchy (L2BM → L1BM → MAB → GRF) gives the compiler a large, fast scratchpad. Explicit data placement across tiers eliminates wasted bandwidth and maximizes compute utilization.
World-Class Power Efficiency
By removing cache controllers, branch predictors, and speculative execution, MN-Core dedicates transistors to compute. The result: higher FLOPS/watt compared to general-purpose GPUs.
MN-Core vs GPU
| Aspect | GPU | MN-Core |
|---|---|---|
| Instruction | Scalar / SIMT | VLIW + SIMD |
| Cache | Hardware-managed (L1/L2) | None — compiler-managed |
| Memory Hierarchy | Implicit (cache) | Explicit (L2BM / L1BM / MAB / GRF) |
| Performance | Varies with cache behavior | Deterministic |
| Programming | CUDA / PyTorch | PyTorch (MLSDK), OpenCL-like/Directive-based API (HPCSDK), or bare-metal ISA |
Hardware Complexity, Hidden by the SDK
MN-Core has no hardware cache — memory scheduling, VLIW instruction packing, and data placement must all be handled explicitly. The compiler stack takes care of all of this. Whether you write PyTorch training loops (MLSDK) or HPC kernels in OpenCL-like/Directive-based API (HPCSDK), the compiler translates your code to optimized MN-Core machine code.
SDK Stack
MN-Core Products
See detailed specifications for each generation: